1. Field of the Invention
This invention relates generally to a circuits and systems for the recovery and regeneration of data and synchronizing clock signals received from a serial transmission channel. More particularly this invention relates to circuits and systems for recovery and regeneration of data and synchronizing clock signals while overcoming skew and jitter within the transmitted data and clock signals.
2. Description of Related Art
As commercial and cable television has migrated to high definition digital transmission, equipment manufacturers have cooperated to create the specifications such as the High-Definition Multimedia Interface (HDMI™) developed by Hitachi, Ltd., Matsushita Electric Industrial Co., Ltd., Philips Consumer Electronics, International B.V., Silicon Image, Inc., Sony Corporation, and Thomson Inc.
Toshiba Corporation, and the digital visual interface (DVI) specification, as promulgated by the Digital Display Working Group, to describe transmitting digital television audiovisual signals from DVD players, cable television set-top boxes and other audiovisual sources to television sets, projectors and other video displays. DVI can carry high quality multi-channel audio data and can carry all standard and high-definition consumer electronics video formats. Further, HDMI™ can also carry control and status information in both directions.
Referring to FIG. 1, HDMI™ system architecture is defined to consist of Sources 5 and Sinks 10. The HDMI™ source device 5 communicates with the over HDMI™ cable and connectors. The HDMI™ cable and connectors carry four differential pairs that make up the Transition Minimized Differential Signaling (TMDS) data and clock channels 15a, 15b, 15c, and 15d. These channels 15a, 15b, 15c, and 15d are used to carry video, audio and auxiliary data. In addition, HDMI™ cables and connectors carry a digital data (DDC) channel 20. The DDC 20 is used for configuration and status exchange between a single Source 5 and a single Sink 10 by reading the Enhanced Extended Display Identification Data (EDID) from the EDID read only memory 40 to retrieve the Sink's configuration and/or capabilities.
The optional Consumer Electronic Control (CEC) line 55 provides high-level control functions between all of the various audiovisual products in a user's environment.
Video 45, audio 50 and auxiliary data is transmitted across the three TMDS data channels 15a, 15b, and 15c. The video pixel clock is transmitted on the TMDS clock channel 15d and is used by the receiver 35 as a frequency reference for data recovery on the three TMDS data channels 15a, 15b, and 15c. Video data is carried as a series of 24-bit pixels on the three TMDS data channels 15a, 15b, and 15c. TMDS encoding converts the 8 bits per channel into the 10 bit DC-balanced, transition minimized sequence which is then transferred by the transmitter 30 serially across the pair at a rate of 10 bits per pixel clock period to the receiver 35. The receiver 35 acquires and recovers the transmitted data and the synchronizing clock of the data to restore the received video data 55 and the audio data 60.
Video pixel rates can range from 25 MHz to 165 MHz. Video formats with rates below 25 MHz (e.g. 13.5 MHz for NTSC) can be transmitted using a pixel-repetition scheme. Up to 24 bits per pixel are transferred. In order to transmit audio and auxiliary data across the TMDS channels 15a, 15b, and 15c, HDMI™ uses a packet structure. In order to attain the higher reliability required of audio and control data, the data is protected with an error correction code and is encoded using a special error reduction coding to produce the 10-bit word that is transmitted
The transmitter 30, as shown in FIG. 2 has three encoder and serializers 32a, 32b, and 32c that receive the video components 45a, 45a, and 45c, the audio components 50a, 50b, and 50c, and the control signals 47a, 47b, 47c, and 47d and convert the signals into the three TMDS link channels 15a, 15b, and 15c. The pixel clock 52 is transmitted on the clock channel 15d to be the received pixel clock 54. It should be noted that the pixel clock 52 is the clock for the complete pixel and the bits of the data packets transmitted on the TMDS link channels 15a, 15b, and 15c are transmitted at a multiple of 10 greater than the pixel clock. The data packets are synchronized by a clock that has a frequency that is ten times greater than the pixel clock 52. For pixel rates at 165 MHz, the serialized bits of the packet data must be transmitted at a rate of 1.65 Gb/S.
To ensure that correct capture of the video and audio data 55 and 60 of FIG. 1, the HDMI™ and DVI specifications include standards for inter-conductor data skew and clock jitter. Correct data capture is ensured at receiving end, in one approach, by data over-sampling followed by selecting a bit from over-sampled bits by decision logic as described in U.S. Pat. No. 5,905,769 (Lee, et al.) and U.S. Pat. No. 6,587,525 (Jeong, et al.). Lee, et al. describes a system that receives a multi-channel digital serial encoded signal and converts the signal into a synchronized set of binary characters. A charge pump phase-locked loop receives a transmitted reference clock and derives a multi-phase clock from the reference clock. The multi-phase clock is used to control a plurality of multi-bit block assembly circuits. Each assembly circuit receives one channel of the digital signal and produces a multi-bit block or character. The multi-bit block assembly circuit includes an oversampler, a digital phase-locked loop and a byte synchronizer. The oversampler oversamples the received digital signal under control of the multiphase clock and produces a sequence of oversampled binary data. The digital phase-locked loop receives the oversampled data and selects samples from it depending on the skew characteristics of the sample. The byte synchronizer assembles a sequence of selected bits into a bit block, or character. An interchannel synchronizer receives as input the characters produced by each of the multi-bit block assembly circuits, and selectively delays output of the received characters in order to synchronize the characters of each channel with one another.
Jeong, et al. describes a system for transmission and recovery of original digital data. The system includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a senders clock to the transmitter and a receiver's clock to the receiver. The transmit clock frequency is a first integer multiple of the system clock frequency, and the receiver clock frequency is a second integer multiple of the transmit clock frequency within 0.1% tolerance. In a normal flow situation, data frames are output by the receiver in alternate cycles of the system clock. In an overflow situation, data frames are output by the receiver in consecutive cycles of the system clock. In an underflow situation, data frames are output by the receiver in non consecutive or alternate cycles of the system clock.
In the over-sampling technique, the decision logic is realized by use of a digital phase lock loop (DPLL) whose phase-pointer is adjusted based on transition (boundary) of the input data so that the phase-pointer always points at the center bit of the over-sampled bits. This approach exhibits deteriorated phase quantization error due to the increased phase interval. When the phase-pointer changes its phase due to change of data boundary, some bits may be selected twice and some may get missed. Therefore careful correction is necessary to remove the repeated bit or add the missing bit, which increases design complexity. Besides, as the clocks and data don't necessarily remain synchronized, error may occur during the over-sampling due to metastability effect. This may cause wrong decision for phase selection in DPLL and result in high bit error rate (BER).
The advantages of the over-sampling technique for data recovery include the high bandwidth of the DPLL to cope with high data rate of the transmitted TMDS data. The over-sampling technique is relatively easy to implement. It employs a small portion of analog circuitry is mostly digital logic circuitry implemented by using standard cells of a typical application specific integrated circuit process flow.
Alternately, the over-sampling technique has a large phase quantization error that requires discrete adjustment. Additional data correction logic is required to correct recovered data error due to the quantization error. Further the over-sampling as described above may cause the sampling faults requiring additional error correction complexity. This added complexity contributes to a large power consumption of the circuits employing the over-sampling technique.
An alternative to the over-sampling technique is the tracking-type of clock and data recovery circuit. The tracking type clock and data recovery circuit is widely used for data rates in the gigabit per second range. The tracking type clock and data recovery circuit applies a delay to the clock for synchronization between data and clock. One application example is given in Japanese Patent Publication JP2001/203676A (Kazutaka, et al.). Kazutaka, et al. provides a circuit in a chip for receiving data synchronously with a clock that takes synchronization between the data and the clock with high accuracy by delaying only the clock without delaying the data. The circuit synchronizes the data and the clock with a first circuit that detects a phase shift between an input data signal and a clock signal. A second circuit converts the detected phase shift into a control voltage for a delay time. A third circuit produces a delay in response to the control voltage to delay the clock and to produce a sampling clock. A fourth circuit receives the input signal in the timing of the sampling clock. Kazutaka, et al. employs the well known Alexander phase detector for synchronization of the recovered clock and data. It is an acceptable approach with reasonable bit error rate at low data rate and relatively easy to achieve high loop bandwidth using voltage controlled delay line for data/clock synchronization; there are no quantization error and Less Sampling Faults.
The tracking-type of clock and data recovery circuit requires very sophisticated control circuitry for the voltage controlled delay line to ensure the sufficient delay variation range for variable data rate used in the TMDS link for applications like DVI or HDMI™. Error or jitter in edge spacing is introduced because of mismatch between the delay lines and their load capacitances. This error or jitter requires large devices and careful layout. Further, the tracking-type of clock and data recovery circuit has less tolerance to asymmetric jitter.
“A 9.9 G-10.8 Gb/S Rate-Adaptive Clock and Data-Recovery with No External Reference Clock for WDM Optical Fiber Transmission”, Noguchi, et al., Digest of Technical Papers: IEEE International Solid-State Circuits Conference, ISSCC-2002, 2002, Volume: 1, pp.: 252-465 describes a 9.9-10.8 Gb/s rate adaptive clock and data recovery circuit with 1:16 DMUX. A dual-input voltage-controlled oscillator incorporates a fast and a slow tracking loop with a DC gain enhancer.
U.S. Patent Application 2004/0210790 (Moon et al.) describes a 0.6-2.5 GBaud CMOS tracked 3× over-sampling clock/data recovery. A wide-range multiphase delay-locked loop (DLL) is used for generation of the multiphase clocks for a serializer in the transmitter. A tracked 3× over-sampling technique with dead-zone phase detection is incorporated in the receiver for clock/data recovery in the presence of excessive jitter and inter-symbol interference (ISI). A voltage-controlled oscillator (VCO), based on a folded starved inverter is used for the clock recovery.
U.S. Patent Application 2004/0042577 (Sumiyoshi et al.) teaches a regenerator circuit extracts proper signals out of signals that have jitter and are skewed. The most stable data rows are selected out of data rows obtained by over-sampling. A serial data regenerator circuit stores serial data as received for two system clocks, compares special character signals used in transmission with the data as stored for two system clocks, and determines positions (shift numbers) where patterns of the data match the special character signal. Correction for skews is implemented by sampling the data on the basis of information on the positions where matching is determined. Correction for jitter and skew is accomplished by three-times over-sampling serial data as received, dividing the serial data as oversampled into three edge groups, detecting a shift number matching special characters for each of the groups by the process described, selecting an edge group undergoing the least change in shift number, and regenerating the serial data from the edge group.
U.S. Pat. No. 6,545,507 (Goller) provides a fast locking clock and data recovery circuit (CDR) with high jitter tolerance and elimination of effects caused by metastability. The CDR circuit provides a fast locking (e.g., within 1.5 sync bit times or the first data transition) clock and data recovery. The CDR circuit takes multiple (e.g., 8) phases of the local clock, which are offset (e.g., by 45 degrees), and uses the multiple phases to latch the state of data at multiple times, and uses the latched data to determine which of the multiple phases captured a data transition. The CDR circuit compares the indicated phase to the phase used to capture a previous data transition and uses such information to produce a stable selection of a clock phase. The selected clock phase is then employed to provide a recovered clock and data signals in association with the incoming serial data stream. The recovered clock and data signals are independent of jitter and free of metastable conditions.